This Blog Documents an alternate implementation of a PDP8e.
The PDP8e is implemented in an ICE40hx8k device. (Lattice Semiconductor)
Verilog has been used to implement the PDP8e. Iverilog is the simulation tool used as well Gtkwave is used to view the results of the simulation. Verilator has been used as a linting tool. The code is compiled with yosys , the Icestorm tools and nextpnr place and route tools.
The implementation currently is the base CPU plus extended memory and the console serial port. The implementation has 8k x 12 bits of memory, using almost all of the memory that is in the ICE40 8k part.
A clock of 60 MHz is used for the logic. It take 4 clocks to execute a machine cycle, there are three types of machine cycles, fetch, defer and execute. On the original PDP8e a amchine cycle took 1.2 microseconds. Here a machine cycle is executed in 4/60 MHz = 67 nanoseconds. This is 17.9 times as fast as the original.
Info: Device utilisation:
Info: ICESTORM_LC: 1285/ 7680 16%
Info: ICESTORM_RAM: 24/ 32 75%
Info: SB_IO: 60/ 256 23%
Info: SB_GB: 6/ 8 75%
Info: ICESTORM_PLL: 1/ 2 50%
Info: SB_WARMBOOT: 0/ 1 0%
Verilog Code to build the FPGA image has been committed to the repository:
https://github.com/armstrong0/PDP8e
Two other repositories hold code to generate the front panel graph and a layout tool for wiring.
https://github.com/armstrong0/PDP8_panel
https://github.com/armstrong0/FPGA_module
Updated the repo. Changed from 4 states per machine cycle to 5 and was able to increase the clock speed to result in a 9 % increase is speed. This code now runs about 20 times faster than the original PDP8e Device utilization has dropped marginally, may just be the way the synthesizer worked. Now uses 1282 ICESTORM_LC, the rest of the resources are the same.
July 20. Updated the repo. Memory extension and USER mode now working. Some hooks in place for EAE
