I just committed working code for the EAE implementation.  This includes both the A and B modes of operation.

 

The logic utilization is:

 ICESTORM_LC:   2258/ 7680    29%
 ICESTORM_RAM:    24/   32    75%
                SB_IO:    60/  256    23%
                SB_GB:     6/    8    75%
ICESTORM_PLL:     1/    2    50%
SB_WARMBOOT:     0/    1     0%

There is still significant room for more!

The division algorithm uses is actually a restoring version rather than the non-restoring version that the original PDP8e used.  

When executing the EAE diagnostics the process was timed, it is currently 19 times faster than the original.  This of course uses a mix of instructions, not just the EAE instructions.  There is probably opportunity to speed up the shift instructions to use a cascade of shifters, 5 in total, rather than up to 23 cycles.    

The ac module has grown significantly during this process.  It is much larger that I would like, but I don't see and easy way to split it up.

 I just committed code that passes al of the hardware tests on hardware.  EXCEPT the EAE tests.

I can now start debugging them.  I would have like to debug in simulations but my computer is not up to it.  It takes too long and I run out of memory.

Some notes on the state machine:

Inputs to the state machine are: 

    instruction

    EAE mode bit

    EAE_loop

    halt

    single step

    continue

    trigger from the front panel

outputs are: 

    current state

The EAE loop signal controls the exit from state EAE1.  The number of times EAE1 loops on itself is a function of the instruction (MUL), sometimes the word following the  instruction, (SHL, ASR, LSR), contents of AC (NMI)

 I have update the code yet again.  The state machine including the EAE is in pretty much its final form.

 This Blog Documents an alternate implementation of a PDP8e.  

The PDP8e is implemented in an ICE40hx8k device.  (Lattice Semiconductor)

Verilog has been used to implement the PDP8e.  Iverilog is the simulation tool used as well Gtkwave is used to view the results of the simulation.  Verilator has been used as a linting tool.  The code is compiled with yosys , the Icestorm tools and nextpnr place and route tools.

The implementation currently is the base CPU plus extended memory and the console serial port.  The implementation has 8k x 12 bits of memory, using almost all of the memory that is in the ICE40 8k part.

A clock of 60 MHz is used for the logic.  It take 4 clocks to execute a machine cycle, there are three types of machine cycles, fetch, defer and execute.  On the original PDP8e a amchine cycle took 1.2 microseconds.  Here a machine cycle is executed in 4/60 MHz = 67 nanoseconds.  This is 17.9 times as fast as the original.

Info: Device utilisation:

Info:         ICESTORM_LC:    1285/ 7680    16%

Info:         ICESTORM_RAM:    24/ 32        75%

Info:         SB_IO:                        60/ 256       23%

Info:         SB_GB:                        6/  8          75%

Info:         ICESTORM_PLL:       1/  2           50%

Info:         SB_WARMBOOT:       0/  1            0%

Verilog Code to build the FPGA image has been committed to the repository:

 https://github.com/armstrong0/PDP8e

Two other repositories hold code to generate the front panel graph and a layout tool for wiring.

https://github.com/armstrong0/PDP8_panel

https://github.com/armstrong0/FPGA_module

Updated the repo.  Changed from 4 states per machine cycle to 5 and was able to increase the clock speed to result in a 9 % increase is speed.  This code now runs about 20 times faster than the original PDP8e  Device utilization has dropped marginally, may just be the way the synthesizer worked.  Now uses 1282 ICESTORM_LC, the rest of the resources are the same.

July 20.  Updated the repo.  Memory extension and USER mode now working.  Some hooks in place for EAE