I have upgraded the memory on this PDP8e.  It is now 10k words.  This takes 30 of the 32 block rams of the FPGA.  I had wanted it to be split into two pieces.  The bottom 8k as it was and the remaining 2k  in the high half of field 7.  However I was unable to convince yosys to do that.  So it is now 10 k continuous.   I could have written a mapper in verilog to remap the 10 k as I described but that would have increased the decoding delay.   The last block rams are unlikely to be able to be used. 

So my plan going forward is to put the binary loader at the upper end of the 2 K section.  This will entail disassembling the binary loader.  Making sure it reassembles to the identical object and then modifying it to reside in field 2 at 37xx - 3777.  At which point I can put it into the FPGA build.  Once there I can use the hardware diagnostics without regard to which ones trash the last page of field 0.  I also want to make the default serial device as the console device.

Going forward from that I should be able to add other bootloaders that can be selected via the switch register for other things like the console serial disk...