I have updated the state diagram, below.  When I started out on this project I had in mind a goal of operating this machine with a 100 MHz clock.  I soon discover that it was not something that was easily accomplished, so I dialed the clock down.  Originally I had 4 states in a machine cycle and each of the machine cycles were identical to that on an original PDP8e.  Once I had thae machine running I realized that the slowest path was reading from memory.  This was caused by the multiplexer at the output of the ram blocks used to select the proper word for reading.  So I added some pipeline  and sped the clock up.  The clock is now running at 73.5 MHz.  If you look at the state diagram you will note there are branches off of state F1, this was added when EAE was added.  Immediate operands for EAE ops are fetched in states F1 and F2(A or B). effectively shortening those operation.  As well when a deferred operation occurs which is not indexed the deferred cycle is only 3 clocks long.   There are other possible changes to the state machine that will increase the speed.