The Max10 does not have enough ram bits to build the full 32768 x 12 ram array.  Some documentation stated that there was more memory than that was actually in the part.  When I tried to infer ram it defaulted to 16384 x 12.  I tried to set the inferred ram size to 4096 x 7 (7 fields of ram).  It still generated 16384 x 12 (4 fields).  The IP catalog has a ram function that let me build a 28672 x 12 array, which I wrapped with verilog to return 0 when to 8 th field is read.  I don't know what happens with writes to that area.

 I have autostart working some of the time.  I am using OS8 boot, if works but not all the time.  The simulation works fine.  I think it is that the power supply for the switches does not come up as fast as the FPGA comes up.  I have added a delay in the code, it has not yet been tested.  I have also added as a build time chioce as Console Serial Device (CSD) boot.

The timing chnages are now inplace and tested on the HX8 FPGA,  I have started building the Max10 platform.  The usual struggles with new, different tools.  Two big items with the Altera build are failure to build the RK8E,it claims that spiRXD has no driver.  Both the simulator and yosys have no problems with it.  

The second problem is ram.  The Max10 has far more ram than the HX8.  It should support 32 k words.  When I specified that it infers ram, but only uses one half of the bits of storage that it should have allocated.